This disclosure relates generally to the field of semiconductor device fabrication, and more particularly to formation of overlapping contacts (or interconnects) for a semiconductor device.
A semiconductor device may include co-planar adjacent contacts that are formed consecutively, during different processing steps. The subsequently formed contacts may need to be electrically connected with one another. FIG. 1 shows a cross-section of an example semiconductor device 100 having an adjacent first contact 102a and second contact 102b according to the prior art. First contact 102a and second contact 102b are formed during different processing steps, i.e., second contact 102b is formed after first contact 102a. First contact 102a and second contact 102b are located adjacent to one another in a dielectric layer 101 which may include an oxide or a nitride. Both the first contact 102a and the second contact 102b include a liner, in this case including a first liner layer 103 and second liner layer 104, and a contact fill metal 105. Electrical connection between the first contact 102a and the second contact 102b only exists at a contact interface 106 at the contact sidewalls. The electrical connection between the first contact 102a and the second contact 102b at contact interface 106 may be poor, as the contact interface 106 has a relatively small area, and may be resistive, as the electrical connection occurs across the liner barriers.